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Routing Congestion in VLSI Circuits: Estimation and Optimization

 
Prashant Saxena (Author) Rupesh S. Shelar (Author) Sachin S. Sapatnekar (Author)
Synopsis

With the dramatic increase in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.

Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.

Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.

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About the author

Prashant Saxena

The author has been pursuing Indian science since a very early age. Brought up in a family of doctors, who themselves are rooted in the ancient Indian wisdom, and having an affinity for science, he has observed closely the evolution of Modern Science and the various holistic perspectives on Indian knowledge. He is also the grandson of Dr. Veerbala, a Sanskrit scholar and a teacher. Professionally, he is a Business Analyst working in an established corporation. He has completed his MBA in Marketing and IT and holds a B.Tech in Computer Science.

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Bibliographic information

Title Routing Congestion in VLSI Circuits: Estimation and Optimization
Format Hardcover
Date published: 31.12.2010
Edition 1st. ed.
Language: English
isbn 9788184893885
length 262p.,