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VHDL: Coding and Logic Synthesis with Synopsys

Authors (s): Weng Fook Lee (Author)
Format: Hardcover
ISBN-13: 9780124406513
Pages: xxiv+392p., Tables; Figures; Glossary; Appendices; Bibliography; Index; 24cm.
Pub. date: 01.01.2000, 1st ed.
Publisher: Academic Press
Language (s): English
Bagchee ID: BB25066
List price: US $ 75,00
Bagchee price: US $ 67,50
You save: (10.00%)
Member price: US $ 60,75 info

Overview for VHDL: Coding and Logic Synthesis with Synopsys

Unlike many other available references, this book is written specifically with practicality in mind. It has over 60 practical examples to help the reader learn how very high-speed integrated hardware description language (VHDL) coding and synthesis can be performed. Starting from simple VHDL coding, the book progresses to complicated, real-world designs. Synthesis results and tweaks are also shown to help the reader gain more insight into how experienced design engineers can optimize any synthesized design. Apart form these key benefits, this book also contains a full chapter dedicated to showing the reader how a full-scale design project of a pipeline microcontroller can be performed: from architecture definition, instruction set definition, micro-architectural implementation, VHDL coding, and testbench coding, to synthesis optimization. In the second portion of the book, synthesis is explained in detail with examples showing the reader how to use Synopsys commands to optimize synthesized designs. This portion of the book also shows the reader many different architectural implementations that can be used to obtain the most efficient design that accomplishes both high-speed performance and minimal area utilization. Many figures are provided throughout this book, including waveforms from simulation results of testbenches. Detailed explanations are provided for these waveforms, easing the learning curve for the reader to understand how VHDL code functions. This is a highly practical book for students, engineers, and anyone wishing to learn how to write synthesizable VHDL code and synthesis using Synopsys.
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